|
Size: 2622
Comment:
|
Size: 2965
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 13: | Line 13: |
| * CacheCoherenceProtocols | |
| Line 27: | Line 28: |
| * DynamicSetOperations | |
| Line 29: | Line 31: |
| * FileSystem (Free BSD) | |
| Line 31: | Line 34: |
| * FirstOrderTheory | |
| Line 38: | Line 42: |
| * GraphTheoryPage | |
| Line 43: | Line 48: |
| * InformationRetrievalSystem | * InformationRetrieval |
| Line 51: | Line 56: |
| * LogicalImplication (|= symbol and also |-) * LogicalMemory |
* LogicalImplication ([[latex2($$\models$$)]] and [[latex2($$\vdash$$)]]) * LogicalMemory (START EDITING HERE) |
| Line 55: | Line 60: |
| * LeastFixedPoint | |
| Line 72: | Line 78: |
| * PresburgerArithmetic | |
| Line 86: | Line 93: |
| * SemiAlgebraicSets | |
| Line 87: | Line 95: |
| * SemiLinearSets | |
| Line 93: | Line 102: |
| * ["taxonomy"] | |
| Line 97: | Line 107: |
| * ["taxonomy"] | * TreeStructures |
| Line 100: | Line 110: |
| * UninterpretedFunctions |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (latex2($$\models$$) and latex2($$\vdash$$))
LogicalMemory (START EDITING HERE)
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula