|
Size: 2680
Comment:
|
Size: 2890
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 28: | Line 28: |
| * DynamicSetOperations | |
| Line 33: | Line 34: |
| * FirstOrderTheory | |
| Line 40: | Line 42: |
| * GraphTheoryPage | |
| Line 45: | Line 48: |
| * InformationRetrievalSystem | * InformationRetrieval |
| Line 57: | Line 60: |
| * LeastFixedPoint | |
| Line 74: | Line 78: |
| * PresburgerArithmetic | |
| Line 88: | Line 93: |
| * SemiAlgebraicSets | |
| Line 89: | Line 95: |
| * SemiLinearSets | |
| Line 95: | Line 102: |
| * ["taxonomy"] | |
| Line 99: | Line 107: |
| * ["taxonomy"] | * TreeStructures |
| Line 102: | Line 110: |
| * UninterpretedFunctions |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula