|
Size: 2722
Comment:
|
Size: 3012
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 19: | Line 19: |
| * ["Cryptography"] | |
| Line 34: | Line 35: |
| * FirstOrderTheory | |
| Line 41: | Line 43: |
| * GraphTheoryPage | |
| Line 54: | Line 57: |
| * LogicalImplication (|= symbol and also |-) * LogicalMemory |
* LogicalImplication ([[latex2($$\models$$)]] and [[latex2($$\vdash$$)]]) * LogicalMemory (START EDITING HERE) |
| Line 58: | Line 61: |
| * LeastFixedPoint | |
| Line 75: | Line 79: |
| * PresburgerArithmetic | |
| Line 89: | Line 94: |
| * SemiAlgebraicSets | |
| Line 90: | Line 96: |
| * SemiLinearSets | |
| Line 94: | Line 101: |
| * ["Steganography"] | |
| Line 104: | Line 112: |
| * UninterpretedFunctions |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
- ["Cryptography"]
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (latex2($$\models$$) and latex2($$\vdash$$))
LogicalMemory (START EDITING HERE)
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Steganography"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula