|
Size: 523
Comment:
|
Size: 2202
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw * AreaBorderRouter |
|
| Line 2: | Line 5: |
| * AutonomousSystem (AS) * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra * BooleanTerm * CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions) |
|
| Line 3: | Line 12: |
| * CpuTime * CyclesPerInstruction (CPI) * ["Decidable"] and SemiDecidable * ["Dichotomy"] * DijkstrasAlgorithm * DelayBandwidthProduct * DisjunctiveSyllogism * DistanceVector * ExecutionTime |
|
| Line 5: | Line 23: |
| * InternetGatewayRoutingProtocol IGRP | * FiveClassicPartsOfaComputer * FixedPoint * ForwardingVsRouting * FrameBuffer * FreeBooleanAlgebra * GeometricMean * GroundClause * GroundBooleanTerm * HammingCode * HardwareDesignPrinciples * HypotheticalSylogism * InteriorGatewayRoutingProtocol (IGRP) |
| Line 7: | Line 36: |
| * InternetProtocolV4 | * InternetProtocolV4 (IPv4) * InternetProtocolV6 (IPv6) |
| Line 9: | Line 39: |
| * InstructionSetArchitecture (ISA) * LogicalImplication (|= symbol and also |-) |
|
| Line 10: | Line 42: |
| * ["Latency"] | |
| Line 11: | Line 44: |
| * LinkerSteps | |
| Line 12: | Line 46: |
| * MaximumTransmissionUnit (MTU) | |
| Line 13: | Line 48: |
| * ModusPonens * MonotoneBooleanTerm * ObjectFile |
|
| Line 14: | Line 52: |
| * OsiModel (7 layer OSI network Model) * ["Performance"] |
|
| Line 15: | Line 55: |
| * PowerSet * ["Proposition"] or PropositionalLogic * ["Processor"] or CPU * QueuingTheory * RecursivelyEnumerableSets * ["Register"] (MIPS register) * RelationallyComplete * ResponseTime * RoutingArea * RoutingInformationProtocol (RIP) |
|
| Line 17: | Line 67: |
| * SemanticsSyntaxSortsInLogic * SemiDecidable and ["Decidable"] * SequenceNumber * SlidingWindowProtocol * SpatialExtent * SpeedUp * ["Tautology"] * TcpFastRetransmit * TcpFastRecovery * ThroughPut * TransmissionControlProtocol (TCP) * ["taxonomy"] |
|
| Line 18: | Line 80: |
| * ["Undecidable"] | |
| Line 19: | Line 82: |
| * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula