| 
  
   Size: 780 
  
  Comment:  
 | 
  
   Size: 3012 
  
  Comment:  
 | 
| Deletions are marked like this. | Additions are marked like this. | 
| Line 1: | Line 1: | 
|    * AddressingModes * AmdahlsLaw * AreaBorderRouter  | 
|
| Line 2: | Line 5: | 
|    * AutonomousSystem (AS) * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra * BooleanTerm * BoothsAlgorithm * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine * CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)  | 
|
| Line 3: | Line 17: | 
|    * CpuTime * CriticalSection * ["Cryptography"] * CyclesPerInstruction (CPI) * DataPath * ["Decidable"] and SemiDecidable * DelayBandwidthProduct * DelayedBranch * ["Dichotomy"]  | 
|
| Line 4: | Line 27: | 
| * DisjunctiveSyllogism | |
| Line 5: | Line 29: | 
|    * DynamicSetOperations * ExecutionTime * ExpectedValue * FileSystem (Free BSD)  | 
|
| Line 7: | Line 35: | 
|    * FirstOrderTheory * FiveClassicPartsOfaComputer * FixedPoint * FloatingPointRepresentation (IEEE 754)  | 
|
| Line 8: | Line 40: | 
|    * FrameBuffer * FreeBooleanAlgebra * GeometricMean * GraphTheoryPage * GroundClause * GroundBooleanTerm * HammingCode * HardwareDesignPrinciples * HypotheticalSylogism * InformationRetrieval  | 
|
| Line 11: | Line 53: | 
| * InternetProtocolV6 (IPv6) | |
| Line 12: | Line 55: | 
|    * InstructionSetArchitecture (ISA) * InvertedFile * LogicalImplication ([[latex2($$\models$$)]] and [[latex2($$\vdash$$)]]) * LogicalMemory (START EDITING HERE)  | 
|
| Line 13: | Line 60: | 
|    * ["Latency"] * LeastFixedPoint  | 
|
| Line 14: | Line 63: | 
| * LinkerSteps | |
| Line 16: | Line 66: | 
|    * MemoryHierarchy * MemoryStallClockCycles  | 
|
| Line 17: | Line 69: | 
| * MultiProtocolLabelSwitching (MPLS) |    * ModusPonens * MonotoneBooleanTerm * ObjectFile  | 
| Line 20: | Line 74: | 
|    * PageTable * ["Performance"] * PipeLine * PostingsFile  | 
|
| Line 21: | Line 79: | 
|    * PresburgerArithmetic * PowerSet * ["Proposition"] or PropositionalLogic * ["Processor"] or CPU * QueuingTheory * RaceCondition * RecursivelyEnumerableSets * ["Register"] (MIPS register) * RelationallyComplete * ResponseTime * RoutingArea  | 
|
| Line 24: | Line 93: | 
|    * SemanticsSyntaxSortsInLogic * SemiAlgebraicSets * SemiDecidable and ["Decidable"] * SemiLinearSets * SequenceNumber * SlidingWindowProtocol * SpatialExtent * SpeedUp * ["Steganography"] * SuperScalar * ["Tautology"]  | 
|
| Line 25: | Line 105: | 
|    * TcpFastRetransmit * TcpFastRecovery * ThroughPut * TransmissionControlProtocol (TCP) * TreeStructures  | 
|
| Line 26: | Line 111: | 
|    * ["Undecidable"] * UninterpretedFunctions  | 
|
| Line 27: | Line 114: | 
|    * VirtualMemory * WallClockTime  | 
AutonomousSystem (AS)
- ["Bijection"]
 CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
- ["Cryptography"]
 CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
 FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (latex2($$\models$$) and latex2($$\vdash$$))
LogicalMemory (START EDITING HERE)
- ["Latency"]
 MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
 OsiModel (7 layer OSI network Model)
- ["Performance"]
 ["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
 - ["Register"] (MIPS register)
 - ["Satisfiable"]
 SemiDecidable and ["Decidable"]
- ["Steganography"]
 - ["Tautology"]
 - ["taxonomy"]
 - ["Undecidable"]
 - ["Valid"] Logic Formula
 
