|
Size: 901
Comment:
|
Size: 2337
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra * BooleanTerm * BoothsAlgorithm * CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions) |
|
| Line 5: | Line 13: |
| * CpuTime * CyclesPerInstruction (CPI) * DataPath * ["Decidable"] and SemiDecidable * ["Dichotomy"] |
|
| Line 6: | Line 19: |
| * DelayBandwidthProduct * DelayedBranch * DisjunctiveSyllogism |
|
| Line 7: | Line 23: |
| * ExecutionTime | |
| Line 9: | Line 26: |
| * FiveClassicPartsOfaComputer * FixedPoint * FloatingPointRepresentation (IEEE 754) |
|
| Line 10: | Line 30: |
| * FrameBuffer * FreeBooleanAlgebra * GeometricMean * GroundClause * GroundBooleanTerm * HammingCode * HardwareDesignPrinciples * HypotheticalSylogism |
|
| Line 15: | Line 43: |
| * InstructionSetArchitecture (ISA) * LogicalImplication (|= symbol and also |-) |
|
| Line 16: | Line 46: |
| * ["Latency"] | |
| Line 17: | Line 48: |
| * LinkerSteps | |
| Line 20: | Line 52: |
| * MultiProtocolLabelSwitching (MPLS) | * ModusPonens * MonotoneBooleanTerm * ObjectFile |
| Line 23: | Line 57: |
| * ["Performance"] * PipeLine |
|
| Line 24: | Line 60: |
| * PowerSet * ["Proposition"] or PropositionalLogic * ["Processor"] or CPU * QueuingTheory * RecursivelyEnumerableSets * ["Register"] (MIPS register) * RelationallyComplete * ResponseTime |
|
| Line 28: | Line 72: |
| * SemanticsSyntaxSortsInLogic * SemiDecidable and ["Decidable"] * SequenceNumber * SlidingWindowProtocol * SpatialExtent * SpeedUp * SuperScalar |
|
| Line 29: | Line 80: |
| * TcpFastRetransmit * TcpFastRecovery * ThroughPut * TransmissionControlProtocol (TCP) |
|
| Line 31: | Line 86: |
| * ["Undecidable"] | |
| Line 32: | Line 88: |
| * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula