|
Size: 1176
Comment:
|
Size: 2202
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra * BooleanTerm |
|
| Line 6: | Line 12: |
| * CpuTime * CyclesPerInstruction (CPI) * ["Decidable"] and SemiDecidable |
|
| Line 8: | Line 17: |
| * DelayBandwidthProduct | |
| Line 10: | Line 20: |
| * ExecutionTime | |
| Line 12: | Line 23: |
| * FiveClassicPartsOfaComputer * FixedPoint |
|
| Line 13: | Line 26: |
| * FrameBuffer * FreeBooleanAlgebra * GeometricMean * GroundClause * GroundBooleanTerm * HammingCode * HardwareDesignPrinciples |
|
| Line 19: | Line 39: |
| * InstructionSetArchitecture (ISA) | |
| Line 21: | Line 42: |
| * ["Latency"] | |
| Line 22: | Line 44: |
| * LinkerSteps | |
| Line 26: | Line 49: |
| * MultiProtocolLabelSwitching (MPLS) | * MonotoneBooleanTerm * ObjectFile |
| Line 29: | Line 53: |
| * ["Performance"] | |
| Line 30: | Line 55: |
| * PowerSet | |
| Line 31: | Line 57: |
| * ["Processor"] or CPU * QueuingTheory * RecursivelyEnumerableSets * ["Register"] (MIPS register) * RelationallyComplete * ResponseTime |
|
| Line 35: | Line 67: |
| * SemanticsSyntaxSortsInLogic * SemiDecidable and ["Decidable"] * SequenceNumber * SlidingWindowProtocol * SpatialExtent * SpeedUp |
|
| Line 36: | Line 74: |
| * TcpFastRetransmit * TcpFastRecovery * ThroughPut * TransmissionControlProtocol (TCP) |
|
| Line 40: | Line 82: |
| * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula