|
Size: 1350
Comment:
|
Size: 2816
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra * BooleanTerm * BoothsAlgorithm * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
| Line 6: | Line 17: |
| * CpuTime * CriticalSection * CyclesPerInstruction (CPI) * DataPath * ["Decidable"] and SemiDecidable * DelayBandwidthProduct * DelayedBranch |
|
| Line 10: | Line 28: |
| * DynamicSetOperations * ExecutionTime * ExpectedValue * FileSystem (Free BSD) |
|
| Line 12: | Line 34: |
| * FirstOrderTheory * FiveClassicPartsOfaComputer |
|
| Line 13: | Line 37: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 14: | Line 39: |
| * FrameBuffer * FreeBooleanAlgebra * GeometricMean * GraphTheoryPage |
|
| Line 15: | Line 44: |
| * GroundBooleanTerm * HammingCode * HardwareDesignPrinciples |
|
| Line 16: | Line 48: |
| * InformationRetrieval | |
| Line 21: | Line 54: |
| * InstructionSetArchitecture (ISA) * InvertedFile |
|
| Line 22: | Line 57: |
| * LogicalMemory | |
| Line 23: | Line 59: |
| * ["Latency"] * LeastFixedPoint |
|
| Line 24: | Line 62: |
| * LinkerSteps | |
| Line 26: | Line 65: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 28: | Line 69: |
| * MultiProtocolLabelSwitching (MPLS) | * MonotoneBooleanTerm * ObjectFile |
| Line 31: | Line 73: |
| * PageTable * ["Performance"] * PipeLine * PostingsFile |
|
| Line 32: | Line 78: |
| * PresburgerArithmetic | |
| Line 34: | Line 81: |
| * ["Processor"] or CPU * QueuingTheory * RaceCondition * RecursivelyEnumerableSets * ["Register"] (MIPS register) * RelationallyComplete * ResponseTime |
|
| Line 39: | Line 93: |
| * SemiDecidable and ["Decidable"] | |
| Line 41: | Line 96: |
| * SpatialExtent * SpeedUp * SuperScalar |
|
| Line 42: | Line 100: |
| * ["taxonomy"] * TcpFastRetransmit * TcpFastRecovery * ThroughPut |
|
| Line 43: | Line 105: |
| * ["taxonomy"] | * TreeStructures |
| Line 47: | Line 109: |
| * VirtualMemory * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula