|
Size: 1485
Comment:
|
Size: 2584
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra * BooleanTerm * BoothsAlgorithm * CaChe * CacheBlock * CacheLine |
|
| Line 6: | Line 16: |
| * CpuTime * CriticalSection * CyclesPerInstruction (CPI) * DataPath |
|
| Line 7: | Line 21: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 11: | Line 27: |
| * ExecutionTime * ExpectedValue |
|
| Line 13: | Line 31: |
| * FiveClassicPartsOfaComputer | |
| Line 14: | Line 33: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 15: | Line 35: |
| * FrameBuffer * FreeBooleanAlgebra * GeometricMean |
|
| Line 16: | Line 39: |
| * GroundBooleanTerm * HammingCode * HardwareDesignPrinciples |
|
| Line 17: | Line 43: |
| * InformationRetrievalSystem | |
| Line 22: | Line 49: |
| * InstructionSetArchitecture (ISA) | |
| Line 23: | Line 51: |
| * LogicalMemory | |
| Line 24: | Line 53: |
| * ["Latency"] | |
| Line 25: | Line 55: |
| * LinkerSteps | |
| Line 27: | Line 58: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 29: | Line 62: |
| * MultiProtocolLabelSwitching (MPLS) | * MonotoneBooleanTerm * ObjectFile |
| Line 32: | Line 66: |
| * PageTable * ["Performance"] * PipeLine |
|
| Line 35: | Line 72: |
| * ["Processor"] or CPU * QueuingTheory * RaceCondition |
|
| Line 36: | Line 76: |
| * ["Register"] (MIPS register) | |
| Line 37: | Line 78: |
| * ResponseTime | |
| Line 45: | Line 87: |
| * SpatialExtent * SpeedUp * SuperScalar |
|
| Line 46: | Line 91: |
| * TcpFastRetransmit * TcpFastRecovery * ThroughPut |
|
| Line 51: | Line 99: |
| * VirtualMemory * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula