|
Size: 1553
Comment:
|
Size: 2622
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime * ["Bijection"] * BooleanAlgebra |
|
| Line 5: | Line 10: |
| * BoothsAlgorithm * CaChe * CacheBlock * CacheLine |
|
| Line 7: | Line 16: |
| * CpuTime * CriticalSection * CyclesPerInstruction (CPI) * DataPath |
|
| Line 8: | Line 21: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 12: | Line 27: |
| * ExecutionTime * ExpectedValue |
|
| Line 14: | Line 31: |
| * FiveClassicPartsOfaComputer | |
| Line 15: | Line 33: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 16: | Line 35: |
| * FrameBuffer * FreeBooleanAlgebra * GeometricMean |
|
| Line 18: | Line 40: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 19: | Line 43: |
| * InformationRetrievalSystem | |
| Line 24: | Line 49: |
| * InstructionSetArchitecture (ISA) * InvertedFile |
|
| Line 25: | Line 52: |
| * LogicalMemory | |
| Line 26: | Line 54: |
| * ["Latency"] | |
| Line 27: | Line 56: |
| * LinkerSteps | |
| Line 29: | Line 59: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 31: | Line 63: |
| * MultiProtocolLabelSwitching (MPLS) | |
| Line 33: | Line 64: |
| * ObjectFile | |
| Line 35: | Line 67: |
| * PageTable * ["Performance"] * PipeLine * PostingsFile |
|
| Line 38: | Line 74: |
| * ["Processor"] or CPU * QueuingTheory * RaceCondition |
|
| Line 39: | Line 78: |
| * ["Register"] (MIPS register) | |
| Line 40: | Line 80: |
| * ResponseTime | |
| Line 48: | Line 89: |
| * SpatialExtent * SpeedUp * SuperScalar |
|
| Line 49: | Line 93: |
| * TcpFastRetransmit * TcpFastRecovery * ThroughPut |
|
| Line 54: | Line 101: |
| * VirtualMemory * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula