| 
  
   Size: 1640 
  
  Comment:  
 | 
  
   Size: 3149 
  
  Comment:  
 | 
| Deletions are marked like this. | Additions are marked like this. | 
| Line 1: | Line 1: | 
|    * AddressingModes * AmdahlsLaw  | 
|
| Line 4: | Line 6: | 
| * ["Bijections"] |    * AverageNormalizedExecutionTime * ["Bijection"]  | 
| Line 7: | Line 10: | 
|    * BoothsAlgorithm * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine  | 
|
| Line 9: | Line 17: | 
|    * CpuTime * CriticalSection * ["Cryptography"] * CutFreeProof * CyclesPerInstruction (CPI) * DataPath  | 
|
| Line 10: | Line 24: | 
|    * DelayBandwidthProduct * DelayedBranch  | 
|
| Line 14: | Line 30: | 
|    * DynamicSetOperations * ExecutionTime * ExpectedValue * FileSystem (Free BSD)  | 
|
| Line 16: | Line 36: | 
|    * FirstOrderTheory * FiveClassicPartsOfaComputer  | 
|
| Line 17: | Line 39: | 
| * FloatingPointRepresentation (IEEE 754) | |
| Line 18: | Line 41: | 
| * FrameBuffer | |
| Line 19: | Line 43: | 
|    * GeometricMean * GraphTheoryPage  | 
|
| Line 21: | Line 47: | 
|    * HammingCode * HardwareDesignPrinciples  | 
|
| Line 22: | Line 50: | 
| * InformationRetrieval | |
| Line 27: | Line 56: | 
| * LogicalImplication (|= symbol and also |-) |    * ["Interpolant"] * InstructionSetArchitecture (ISA) * InterfaceMessagingProcessor (IMP) * InvertedFile * LogicalImplication ([[latex2($$\models$$)]] and [[latex2($$\vdash$$)]]) * LogicalMemory (START EDITING HERE)  | 
| Line 29: | Line 63: | 
|    * ["Latency"] * LeastFixedPoint  | 
|
| Line 30: | Line 66: | 
| * LinkerSteps | |
| Line 32: | Line 69: | 
|    * MemoryHierarchy * MemoryStallClockCycles  | 
|
| Line 34: | Line 73: | 
| * MultiProtocolLabelSwitching (MPLS) | |
| Line 36: | Line 74: | 
| * ObjectFile | |
| Line 38: | Line 77: | 
|    * PageTable * ["Performance"] * PipeLine * PostingsFile  | 
|
| Line 39: | Line 82: | 
| * PresburgerArithmetic | |
| Line 41: | Line 85: | 
|    * ["Processor"] or CPU * QueuingTheory * RaceCondition  | 
|
| Line 42: | Line 89: | 
| * ["Register"] (MIPS register) | |
| Line 43: | Line 91: | 
| * ResponseTime | |
| Line 48: | Line 97: | 
| * SemiAlgebraicSets | |
| Line 49: | Line 99: | 
| * SemiLinearSets | |
| Line 52: | Line 103: | 
|    * SpeedUp * ["Steganography"] * SuperScalar  | 
|
| Line 53: | Line 107: | 
|    * ["taxonomy"] * TcpFastRetransmit * TcpFastRecovery * ThroughPut  | 
|
| Line 54: | Line 112: | 
| * ["taxonomy"] |    * TreeStructures * TruthFunction (notation for [[latex2($\vdash$)]])  | 
| Line 57: | Line 116: | 
| * UninterpretedFunctions | |
| Line 58: | Line 118: | 
|    * VirtualMemory * WallClockTime  | 
AutonomousSystem (AS)
- ["Bijection"]
 CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
- ["Cryptography"]
 CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
 FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
- ["Interpolant"]
 LogicalImplication (latex2($$\models$$) and latex2($$\vdash$$))
LogicalMemory (START EDITING HERE)
- ["Latency"]
 MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
 OsiModel (7 layer OSI network Model)
- ["Performance"]
 ["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
 - ["Register"] (MIPS register)
 - ["Satisfiable"]
 SemiDecidable and ["Decidable"]
- ["Steganography"]
 - ["Tautology"]
 - ["taxonomy"]
 TruthFunction (notation for latex2($\vdash$))
- ["Undecidable"]
 - ["Valid"] Logic Formula
 
