|
Size: 1749
Comment:
|
Size: 2531
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime | |
| Line 7: | Line 10: |
| * BoothsAlgorithm * CaChe * CacheBlock * CacheLine |
|
| Line 9: | Line 16: |
| * CpuTime * CriticalSection * CyclesPerInstruction (CPI) * DataPath |
|
| Line 10: | Line 21: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 12: | Line 25: |
| * DelayBandwidthProduct | |
| Line 15: | Line 27: |
| * ExecutionTime | |
| Line 17: | Line 30: |
| * FiveClassicPartsOfaComputer | |
| Line 18: | Line 32: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 19: | Line 34: |
| * FrameBuffer | |
| Line 20: | Line 36: |
| * GeometricMean | |
| Line 22: | Line 39: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 28: | Line 47: |
| * InstructionSetArchitecture (ISA) | |
| Line 29: | Line 49: |
| * LogicalMemory | |
| Line 30: | Line 51: |
| * ["Latency"] | |
| Line 31: | Line 53: |
| * LinkerSteps | |
| Line 33: | Line 56: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 35: | Line 60: |
| * MultiProtocolLabelSwitching (MPLS) | |
| Line 37: | Line 61: |
| * ObjectFile | |
| Line 39: | Line 64: |
| * PageTable | |
| Line 40: | Line 66: |
| * PipeLine | |
| Line 43: | Line 70: |
| * ["Processor"] or CPU * QueuingTheory * RaceCondition |
|
| Line 44: | Line 74: |
| * ["Register"] (MIPS register) | |
| Line 45: | Line 76: |
| * ResponseTime | |
| Line 55: | Line 87: |
| * SuperScalar | |
| Line 58: | Line 91: |
| * ThroughPut | |
| Line 63: | Line 97: |
| * VirtualMemory * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula