|
Size: 1749
Comment:
|
Size: 2046
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AmdahlsLaw | |
| Line 4: | Line 5: |
| * AverageNormalizedExecutionTime | |
| Line 9: | Line 11: |
| * CpuTime | |
| Line 15: | Line 18: |
| * ExecutionTime | |
| Line 17: | Line 21: |
| * FiveClassicPartsOfaComputer | |
| Line 19: | Line 24: |
| * FrameBuffer | |
| Line 20: | Line 26: |
| * GeometricMean | |
| Line 22: | Line 29: |
| * HammingCode | |
| Line 28: | Line 36: |
| * InstructionSetArchitecture (ISA) | |
| Line 30: | Line 39: |
| * ["Latency"] | |
| Line 35: | Line 45: |
| * MultiProtocolLabelSwitching (MPLS) | |
| Line 43: | Line 52: |
| * ["Processor"] or CPU * QueuingTheory |
|
| Line 45: | Line 56: |
| * ResponseTime | |
| Line 58: | Line 70: |
| * ThroughPut | |
| Line 63: | Line 76: |
| * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
["Decidable"] and SemiDecidable
- ["Dichotomy"]
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula