|
Size: 1808
Comment:
|
Size: 2377
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime | |
| Line 7: | Line 10: |
| * BoothsAlgorithm | |
| Line 9: | Line 13: |
| * CpuTime * CyclesPerInstruction (CPI) * DataPath |
|
| Line 13: | Line 20: |
| * DelayedBranch | |
| Line 18: | Line 26: |
| * FiveClassicPartsOfaComputer | |
| Line 19: | Line 28: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 20: | Line 30: |
| * FrameBuffer | |
| Line 21: | Line 32: |
| * GeometricMean | |
| Line 23: | Line 35: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 29: | Line 43: |
| * InstructionSetArchitecture (ISA) | |
| Line 30: | Line 45: |
| * LogicalMemory | |
| Line 31: | Line 47: |
| * ["Latency"] | |
| Line 32: | Line 49: |
| * LinkerSteps | |
| Line 36: | Line 54: |
| * MultiProtocolLabelSwitching (MPLS) | |
| Line 38: | Line 55: |
| * ObjectFile | |
| Line 41: | Line 59: |
| * PipeLine | |
| Line 44: | Line 63: |
| * ["Processor"] or CPU | |
| Line 46: | Line 66: |
| * ["Register"] (MIPS register) | |
| Line 58: | Line 79: |
| * SuperScalar | |
| Line 61: | Line 83: |
| * ThroughPut | |
| Line 66: | Line 89: |
| * VirtualMemory * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula