|
Size: 1802
Comment:
|
Size: 3071
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| * AddressingModes * AmdahlsLaw |
|
| Line 4: | Line 6: |
| * AverageNormalizedExecutionTime | |
| Line 7: | Line 10: |
| * BoothsAlgorithm * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
| Line 9: | Line 17: |
| * CpuTime * CriticalSection * ["Cryptography"] * CutFreeProof * CyclesPerInstruction (CPI) * DataPath |
|
| Line 10: | Line 24: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 12: | Line 28: |
| * DelayBandwidthProduct | |
| Line 15: | Line 30: |
| * DynamicSetOperations | |
| Line 16: | Line 32: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 18: | Line 36: |
| * FirstOrderTheory * FiveClassicPartsOfaComputer |
|
| Line 19: | Line 39: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 20: | Line 41: |
| * FrameBuffer | |
| Line 21: | Line 43: |
| * GeometricMean * GraphTheoryPage |
|
| Line 23: | Line 47: |
| * HammingCode * HardwareDesignPrinciples |
|
| Line 24: | Line 50: |
| * InformationRetrieval | |
| Line 29: | Line 56: |
| * LogicalImplication (|= symbol and also |-) | * InstructionSetArchitecture (ISA) * InterfaceMessagingProcessor (IMP) * InvertedFile * LogicalImplication ([[latex2($$\models$$)]] and [[latex2($$\vdash$$)]]) * LogicalMemory (START EDITING HERE) |
| Line 32: | Line 63: |
| * LeastFixedPoint | |
| Line 33: | Line 65: |
| * LinkerSteps | |
| Line 35: | Line 68: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 38: | Line 73: |
| * ObjectFile | |
| Line 40: | Line 76: |
| * PageTable | |
| Line 41: | Line 78: |
| * PipeLine * PostingsFile |
|
| Line 42: | Line 81: |
| * PresburgerArithmetic | |
| Line 44: | Line 84: |
| * ["Processor"] or CPU | |
| Line 45: | Line 86: |
| * RaceCondition | |
| Line 46: | Line 88: |
| * ["Register"] (MIPS register) | |
| Line 53: | Line 96: |
| * SemiAlgebraicSets | |
| Line 54: | Line 98: |
| * SemiLinearSets | |
| Line 58: | Line 103: |
| * ["Steganography"] * SuperScalar |
|
| Line 59: | Line 106: |
| * ["taxonomy"] | |
| Line 63: | Line 111: |
| * ["taxonomy"] | * TreeStructures |
| Line 66: | Line 114: |
| * UninterpretedFunctions | |
| Line 67: | Line 116: |
| * VirtualMemory * WallClockTime |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
- ["Cryptography"]
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (latex2($$\models$$) and latex2($$\vdash$$))
LogicalMemory (START EDITING HERE)
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Steganography"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula