Diff for "ComputerTerms"

Differences between revisions 77 and 109 (spanning 32 versions)

AddressingModes
AmdahlsLaw
AreaBorderRouter
AffineMotion
AutonomousSystem (AS)
AverageNormalizedExecutionTime
["Bijection"]
BooleanAlgebra
BooleanTerm
BoothsAlgorithm
CaChe
CacheBlock
CacheLine
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CpuTime
CriticalSection
CyclesPerInstruction (CPI)
DataPath
["Decidable"] and SemiDecidable
DelayBandwidthProduct
DelayedBranch
["Dichotomy"]
DijkstrasAlgorithm
DisjunctiveSyllogism
DistanceVector
ExecutionTime
ExpectedValue
FirstOrderPredicateLogic
FirstOrderPredicateLogicQuatifiers
FiveClassicPartsOfaComputer
FixedPoint
FloatingPointRepresentation (IEEE 754)
ForwardingVsRouting
FrameBuffer
FreeBooleanAlgebra
GeometricMean
GroundClause
GroundBooleanTerm
HammingCode
HardwareDesignPrinciples
HypotheticalSylogism
InformationRetrievalSystem
InteriorGatewayRoutingProtocol (IGRP)
InterNet
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
InternetWork
InstructionSetArchitecture (ISA)
LogicalImplication (|= symbol and also
LogicalMemory
IpCheckSum
["Latency"]
LinearlyDecomposableDomains
LinkerSteps
LinkState
MaximumTransmissionUnit (MTU)
MemoryHierarchy
MemoryStallClockCycles
["Model"] of a logic formula
ModusPonens
MonotoneBooleanTerm
ObjectFile
OpenShortestPathFirst OSPF
OsiModel (7 layer OSI network Model)
PageTable
["Performance"]
PipeLine
PredicateSymbols
PowerSet
["Proposition"] or PropositionalLogic
["Processor"] or CPU
QueuingTheory
RaceCondition
RecursivelyEnumerableSets
["Register"] (MIPS register)
RelationallyComplete
ResponseTime
RoutingArea
RoutingInformationProtocol (RIP)
RoutingPathologies
["Satisfiable"]
SemanticsSyntaxSortsInLogic
SemiDecidable and ["Decidable"]
SequenceNumber
SlidingWindowProtocol
SpatialExtent
SpeedUp
SuperScalar
["Tautology"]
TcpFastRetransmit
TcpFastRecovery
ThroughPut
TransmissionControlProtocol (TCP)
["taxonomy"]
UnaryConstraintDomain
["Undecidable"]
["Valid"] Logic Formula
VirtualMemory
WallClockTime

-  ⇤ ← Revision 77 as of 2004-01-25 17:52:43 → 
  Size: 1893
  Editor: yakko
  Comment:
+   ← Revision 109 as of 2004-03-23 19:02:51 → ⇥
  Size: 2584
  Editor: yakko
  Comment:
-Deletions are marked like this.
+Additions are marked like this.
 Line 1:
+   * AddressingModes
   * AmdahlsLaw
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+Line 10:
+   * BoothsAlgorithm
   * CaChe
   * CacheBlock
   * CacheLine
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+Line 17:
+   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
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+Line 21:
+   * DelayBandwidthProduct
   * DelayedBranch
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+Line 25:
-   * DelayBandwidthProduct
-Line 18:
+Line 28:
+   * ExpectedValue
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+Line 31:
+   * FiveClassicPartsOfaComputer
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+Line 33:
+   * FloatingPointRepresentation (IEEE 754)
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+Line 35:
+   * FrameBuffer
-Line 26:
+Line 40:
+   * HammingCode
   * HardwareDesignPrinciples
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+Line 43:
+   * InformationRetrievalSystem
-Line 32:
+Line 49:
+   * InstructionSetArchitecture (ISA)
-Line 33:
+Line 51:
+   * LogicalMemory
-Line 36:
+Line 55:
+   * LinkerSteps
-Line 38:
+Line 58:
+   * MemoryHierarchy
   * MemoryStallClockCycles
-Line 41:
+Line 63:
+   * ObjectFile
-Line 43:
+Line 66:
+   * PageTable
-Line 44:
+Line 68:
+   * PipeLine
-Line 47:
+Line 72:
+   * ["Processor"] or CPU
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+Line 74:
+   * RaceCondition
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+Line 76:
+   * ["Register"] (MIPS register)
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+Line 89:
+   * SuperScalar
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+Line 99:
+   * VirtualMemory