Differences between revisions 80 and 108 (spanning 28 versions)
Revision 80 as of 2004-02-16 20:16:42
Size: 1946
Editor: velociraptor
Comment:
Revision 108 as of 2004-03-22 18:04:17
Size: 2551
Editor: yakko
Comment:
Deletions are marked like this. Additions are marked like this.
Line 1: Line 1:
   * AddressingModes
Line 9: Line 10:
   * BoothsAlgorithm
   * CaChe
   * CacheBlock
   * CacheLine
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   * CriticalSection
   * CyclesPerInstruction (CPI)
   * DataPath
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   * DelayBandwidthProduct
   * DelayedBranch
Line 15: Line 25:
   * DelayBandwidthProduct
Line 19: Line 28:
   * ExpectedValue
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   * FiveClassicPartsOfaComputer
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   * FloatingPointRepresentation (IEEE 754)
Line 29: Line 41:
   * HardwareDesignPrinciples
Line 35: Line 48:
   * InstructionSetArchitecture (ISA)
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   * LogicalMemory
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   * LinkerSteps
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   * MemoryHierarchy
   * MemoryStallClockCycles
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   * ObjectFile
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   * PageTable
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   * PipeLine
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   * ["Processor"] or CPU
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   * RaceCondition
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   * ["Register"] (MIPS register)
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   * SuperScalar
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   * VirtualMemory

ComputerTerms (last edited 2020-02-02 17:49:07 by scot)