|
Size: 2202
Comment:
|
Size: 3012
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 10: | Line 10: |
| * BoothsAlgorithm * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
| Line 13: | Line 18: |
| * CriticalSection * ["Cryptography"] |
|
| Line 14: | Line 21: |
| * DataPath | |
| Line 15: | Line 23: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 17: | Line 27: |
| * DelayBandwidthProduct | |
| Line 20: | Line 29: |
| * DynamicSetOperations | |
| Line 21: | Line 31: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 23: | Line 35: |
| * FirstOrderTheory | |
| Line 25: | Line 38: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 29: | Line 43: |
| * GraphTheoryPage | |
| Line 34: | Line 49: |
| * InformationRetrieval | |
| Line 40: | Line 56: |
| * LogicalImplication (|= symbol and also |-) | * InvertedFile * LogicalImplication ([[latex2($$\models$$)]] and [[latex2($$\vdash$$)]]) * LogicalMemory (START EDITING HERE) |
| Line 43: | Line 61: |
| * LeastFixedPoint | |
| Line 47: | Line 66: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 53: | Line 74: |
| * PageTable | |
| Line 54: | Line 76: |
| * PipeLine * PostingsFile |
|
| Line 55: | Line 79: |
| * PresburgerArithmetic | |
| Line 59: | Line 84: |
| * RaceCondition | |
| Line 68: | Line 94: |
| * SemiAlgebraicSets | |
| Line 69: | Line 96: |
| * SemiLinearSets | |
| Line 73: | Line 101: |
| * ["Steganography"] * SuperScalar |
|
| Line 74: | Line 104: |
| * ["taxonomy"] | |
| Line 78: | Line 109: |
| * ["taxonomy"] | * TreeStructures |
| Line 81: | Line 112: |
| * UninterpretedFunctions | |
| Line 82: | Line 114: |
| * VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
- ["Cryptography"]
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (latex2($$\models$$) and latex2($$\vdash$$))
LogicalMemory (START EDITING HERE)
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Steganography"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula