|
Size: 2224
Comment:
|
Size: 2551
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 11: | Line 11: |
| * CaChe * CacheBlock * CacheLine |
|
| Line 14: | Line 17: |
| * CriticalSection | |
| Line 15: | Line 19: |
| * DataPath | |
| Line 16: | Line 21: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 18: | Line 25: |
| * DelayBandwidthProduct | |
| Line 22: | Line 28: |
| * ExpectedValue | |
| Line 26: | Line 33: |
| * FloatingPointRepresentation (IEEE 754) | |
| Line 42: | Line 50: |
| * LogicalMemory | |
| Line 48: | Line 57: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 54: | Line 65: |
| * PageTable | |
| Line 55: | Line 67: |
| * PipeLine | |
| Line 60: | Line 73: |
| * RaceCondition | |
| Line 74: | Line 88: |
| * SuperScalar | |
| Line 83: | Line 98: |
| * VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula