|
Size: 2317
Comment:
|
Size: 3052
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 11: | Line 11: |
| * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
| Line 14: | Line 18: |
| * CriticalSection * ["Cryptography"] |
|
| Line 17: | Line 23: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 19: | Line 27: |
| * DelayBandwidthProduct | |
| Line 22: | Line 29: |
| * DynamicSetOperations | |
| Line 23: | Line 31: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 25: | Line 35: |
| * FirstOrderTheory | |
| Line 32: | Line 43: |
| * GraphTheoryPage | |
| Line 37: | Line 49: |
| * InformationRetrieval | |
| Line 43: | Line 56: |
| * LogicalImplication (|= symbol and also |-) | * InterfaceMessagingProcessor (IMP) * InvertedFile * LogicalImplication ([[latex2($$\models$$)]] and [[latex2($$\vdash$$)]]) * LogicalMemory (START EDITING HERE) |
| Line 46: | Line 62: |
| * LeastFixedPoint | |
| Line 50: | Line 67: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 56: | Line 75: |
| * PageTable | |
| Line 58: | Line 78: |
| * PostingsFile | |
| Line 59: | Line 80: |
| * PresburgerArithmetic | |
| Line 63: | Line 85: |
| * RaceCondition | |
| Line 72: | Line 95: |
| * SemiAlgebraicSets | |
| Line 73: | Line 97: |
| * SemiLinearSets | |
| Line 77: | Line 102: |
| * ["Steganography"] | |
| Line 79: | Line 105: |
| * ["taxonomy"] | |
| Line 83: | Line 110: |
| * ["taxonomy"] | * TreeStructures |
| Line 86: | Line 113: |
| * UninterpretedFunctions | |
| Line 87: | Line 115: |
| * VirtualMemory |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
- ["Cryptography"]
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (latex2($$\models$$) and latex2($$\vdash$$))
LogicalMemory (START EDITING HERE)
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Steganography"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula