|
Size: 2393
Comment:
|
Size: 3012
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 11: | Line 11: |
| * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
|
| Line 14: | Line 18: |
| * CriticalSection * ["Cryptography"] |
|
| Line 17: | Line 23: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 19: | Line 27: |
| * DelayBandwidthProduct * DelayedBranch |
|
| Line 23: | Line 29: |
| * DynamicSetOperations | |
| Line 24: | Line 31: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 26: | Line 35: |
| * FirstOrderTheory | |
| Line 33: | Line 43: |
| * GraphTheoryPage | |
| Line 38: | Line 49: |
| * InformationRetrieval | |
| Line 44: | Line 56: |
| * LogicalImplication (|= symbol and also |-) * LogicalMemory |
* InvertedFile * LogicalImplication ([[latex2($$\models$$)]] and [[latex2($$\vdash$$)]]) * LogicalMemory (START EDITING HERE) |
| Line 48: | Line 61: |
| * LeastFixedPoint | |
| Line 52: | Line 66: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 61: | Line 77: |
| * PostingsFile | |
| Line 62: | Line 79: |
| * PresburgerArithmetic | |
| Line 66: | Line 84: |
| * RaceCondition | |
| Line 75: | Line 94: |
| * SemiAlgebraicSets | |
| Line 76: | Line 96: |
| * SemiLinearSets | |
| Line 80: | Line 101: |
| * ["Steganography"] | |
| Line 82: | Line 104: |
| * ["taxonomy"] | |
| Line 86: | Line 109: |
| * ["taxonomy"] | * TreeStructures |
| Line 89: | Line 112: |
| * UninterpretedFunctions |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
- ["Cryptography"]
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (latex2($$\models$$) and latex2($$\vdash$$))
LogicalMemory (START EDITING HERE)
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Steganography"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula