|
Size: 2409
Comment:
|
Size: 2861
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 11: | Line 11: |
| * ["Cache"] | * CaChe * CacheBlock * CacheCoherenceProtocols * CacheLine |
| Line 15: | Line 18: |
| * CriticalSection | |
| Line 24: | Line 28: |
| * DynamicSetOperations | |
| Line 25: | Line 30: |
| * ExpectedValue * FileSystem (Free BSD) |
|
| Line 27: | Line 34: |
| * FirstOrderTheory | |
| Line 34: | Line 42: |
| * GraphTheoryPage | |
| Line 39: | Line 48: |
| * InformationRetrieval | |
| Line 45: | Line 55: |
| * InvertedFile | |
| Line 49: | Line 60: |
| * LeastFixedPoint | |
| Line 53: | Line 65: |
| * MemoryHierarchy * MemoryStallClockCycles |
|
| Line 62: | Line 76: |
| * PostingsFile | |
| Line 63: | Line 78: |
| * PresburgerArithmetic | |
| Line 67: | Line 83: |
| * RaceCondition | |
| Line 76: | Line 93: |
| * SemiAlgebraicSets | |
| Line 77: | Line 95: |
| * SemiLinearSets | |
| Line 83: | Line 102: |
| * ["taxonomy"] | |
| Line 87: | Line 107: |
| * ["taxonomy"] | * TreeStructures |
AutonomousSystem (AS)
- ["Bijection"]
CidrVsSubnetting (CIDR, Subnetting and Class A-E Definitions)
CompleteLogic What does it mean for a logic to be complete
CyclesPerInstruction (CPI)
["Decidable"] and SemiDecidable
- ["Dichotomy"]
FileSystem (Free BSD)
FloatingPointRepresentation (IEEE 754)
InternetProtocolV4 (IPv4)
InternetProtocolV6 (IPv6)
LogicalImplication (|= symbol and also
- ["Latency"]
MaximumTransmissionUnit (MTU)
- ["Model"] of a logic formula
OsiModel (7 layer OSI network Model)
- ["Performance"]
["Proposition"] or PropositionalLogic
- ["Processor"] or CPU
- ["Register"] (MIPS register)
- ["Satisfiable"]
SemiDecidable and ["Decidable"]
- ["Tautology"]
- ["taxonomy"]
- ["Undecidable"]
- ["Valid"] Logic Formula